Two stages in the creation of integrated circuits--logic design and the layout of circuit components--are heavily interrelated. There are a variety of different design and layout methodologies in use today, each with its corresponding advantages and disadvantages. Some emphasize ease of design and/or modification of the logic/layout of the chip, while others emphasize maximum overall chip density.
Gate arrays, for example, provide logic designers with a large degree of flexibility, both for producing initial logic designs and for later modifying those designs to alter functionality or simply to fix bugs. Gate arrays achieve this degree of flexibility by providing a large number of individual gate resources, each of which has already been fabricated up to but not including the final few mask layers.
With gate arrays, the layout process is greatly simplified. The designer simply connects the gate elements on the uppermost few mask layers utilizing a standard design technique often referred to as "late mask programming." Generally, connections on the top three chip layers (two metal layers and the via between them) may be modified, though sometimes a fourth layer (connecting the lower metal layer and the active gate elements themselves) may also be modified.
Late mask programming, however, includes modifications to virtually any mask layers involved in later "interconnection" steps of the integrated circuit fabrication process. When modifications are required (whether due to design changes or the discovery of bugs), the designer merely alters these layers of the integrated circuit, avoiding the significant time and expense which would be required to modify the layout of additional chip layers.
A significant disadvantage results, however, from the fact that the gate array itself, including the individual resources repeated throughout the array, is not customized for any particular logic design. Many gates may therefore be unused in any particular design, resulting in lower chip density due to this inefficient use of space.
So-called "channelless" gate arrays reduce the amount of wasted space by permitting the routing of connections over the gate resources themselves rather than requiring dedicated space in between these resources. See, e.g., Hui et al., "A 4.1K Gates Double Metal HCMOS Sea of Gates Array," IEEE 1985 Custom Integrated Circuits Conference, June, 1985, pp. 15-17; LSI Semiconductor Device and Fabrication Thereof, Balyoz et al., U.S. Pat. No. 4,249,193, Feb. 3, 1981.
Although the channelless technique yields significant improvements in density over the traditional gate array approach, this technique (because it is not customized for a particular design) still inevitably results in unused resources and hence wasted space. Such wasted space leaves less room for minimizing the size of active transistor elements, thereby resulting in greater chip area dedicated to routing, and hence slower performance.
One alternative to using gate arrays is to use previously created libraries of standard cells. One significant advantage to such an approach is the greater density achieved within each standard cell itself (although not within the channels dedicated to routing connections among standard cells). It is not difficult to understand why a custom 4-bit counter cell, for example, is far more dense than the equivalent counter designed with a gate array Knowing in advance which transistors will be used for a desired function yields significantly greater density.
Standard cell design techniques, however, create at least two significant problems First, although each standard cell is quite dense, the design of complex functions requires that significant space on the integrated circuit be allocated to route connections among such standard cells. The space dedicated to routing channels often exceeds (for complex functions) the space dedicated to the functional units (e.g., transistors) themselves.
A channelless approach to standard cell design (analogous to that employed with gate arrays) results in a minor increase in density, although not nearly of the significance of the density increases yielded by channelless gate arrays. See Raza et al., "Channelless Architecture: A New Approach For CMOS Standard Cell Design," IEEE 1985 Custom Integrated Circuits Conference, June, 1985, pp. 12-14 for a discussion of channelless standard cell design.
The relatively minor density improvement yielded by channelless standard cells can be explained by the difference between gate array and standard cell design. Small areas at the boundaries of standard cells are used for routing, rather than creating dedicated routing channels between cells. While this approach yields some improvement in density, little room for improvement remains within each individual cell due to the customized design of each such cell. In other words, traditional gate arrays leave far greater room for density improvements than do standard cells, because individual gate resources can simply be moved up to replace formerly dedicated routing channels in places where (after the functionality has been determined) little routing actually occurs.
A second disadvantage to standard cell design techniques is the limited ability to achieve changes in functionality when bugs are found or functional modifications are desired. Aside from modifying the routing between cells, little room for functional changes exists. Making even slight modifications to a hand-crafted standard cell is quite difficult, and often requires that many layers of the cell be laid out again from scratch.
Another design alternative, and one which significantly increases chip density, is to create a fully customized layout for each integrated circuit. Not surprisingly, custom integrated circuits are difficult both to design and to modify, and thus require significantly more time and expense than either gate array or standard cell design methods.
A cheaper, more flexible alternative to custom designs is the logic array. Logic arrays provide flexibility comparable to that of gate arrays, but in a different manner. Logic arrays facilitate (some to a greater extent than others) the creation of "distributed functionality"--i.e., functions, such as logic gates, whose inputs, outputs and functional units (e.g., transistors) are distributed throughout the integrated circuit, as opposed to being self-contained within a discrete area, as in a gate array.
The concept of distributed functionality is quite important because it enables the logic designer to vary the number, and often the location, of inputs, outputs and functional elements. Typical logic arrays such as PLAs and PALs, however, permit relatively little distribution of functionality. Although the number and location of the inputs to individual gates along each row of the "AND" and "OR" arrays can be modified, the entire length of an array row is utilized whether it forms a two-input or a ten-input AND/OR gate. Moreover, the gate resources themselves cannot be relocated throughout the array, nor can functional distribution beyond the "gate level" be achieved (because each "sum of products" occupies an entire row and column of the array, the result of which must be fed back into the array, if possible, as an input).
Another type of logic array, however, known as a storage logic array or SLA, enables a more significant distribution of functionality than is possible with a PLA or PAL. SLAs permit the AND and OR arrays to be interleaved. In addition, SLAs provide means for segmenting the array's rows and columns, as well as for connecting storage elements to any row/column segment. These features dramatically increase design ease, not by limiting flexibility, but by permitting the creation of isolated functionality, such that intermediate results of computations may be utilized within other portions of the array itself. See, e.g., Storage/Logic Array, Patil, U.S. Pat. No. 4,293,783, Oct. 6, 1981; Asynchronous Logic Array, Patil, U.S. Pat. No. RE No. 31,287, Jun. 21, 1983; Storage Cells For Use in Two Conductor Data Column Storage Logic Arrays, Knapp et al., U.S. Pat. No. 4,442,508, Apr. 10, 1984; Storage Logic Array Having Two Conductor Data Column, Knapp et al., U.S. Pat. No. 4,414,547, Nov. 8, 1983.
SLAs can, of course, be utilized in the same manner as are PLAs and PALs, with the added benefits of achieving isolated functionality (by segmenting array rows and columns) and faster feedback mechanisms (by employing storage elements within the array itself, rather than merely along the periphery). But, adoption of the SLA approach does not in and of itself yield integrated circuits with densities approaching that of custom designs.
What is needed to achieve such densities is an implementation of the basic SLA approach which permits functionality not only to be isolated within discrete areas of the array, but also to be distributed throughout that area (or perhaps throughout the entire array itself).
Although others have in the past considered applying SLA to other technologies, such as the static CMOS technology employed in the preferred embodiment of this invention, such approaches have previously been analyzed from a limited, local perspective, and thus thought to yield insufficient densities. See, e.g., Smith, Kent F., "Design of Regular Arrays Using CMOS in PPL, 1983 IEEE International Conference on Computer Design/VLSI in Computers," Oct. 31, 1983-Nov. 3, 1983. In fact, as is demonstrated below, the use of static CMOS technology not only provides for low power usage, high speed and relatively high noise immunity, but also yields global densities formerly achieved only with hand-crafted, custom designs.